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CY25811/12/14
Spread Spectrum Clock Generator
Features

Applications

4 to 32 MHz input frequency range 4 to 128 MHz output frequency range Accepts clock, crystal, and resonator inputs 1x, 2x, and 4x frequency multiplication: CY25811: 1x; CY25812: 2x; CY25814: 4x Center and down spread modulation Low power dissipation: 3.3V = 52 mW-typ at 6 MHz 3.3V = 60 mW-typ at12 MHz 3.3V = 72 mW-typ at 24 MHz Low cycle to cycle jitter: 8 MHz = 480 ps-max 16 MHz = 400 ps-max 32 MHz = 450 ps-max Available in 8 pin SOIC and TSSOP packages Commercial and industrial temperature ranges
Printers and MFPs LCD panels Digital copiers PDAs CD-ROM, VCD, and DVD Networking, LAN/WAN Scanners Modems Embedded digital systems

Benefits

Peak EMI reduction by 8 to 16 dB Fast time to market Cost reduction

Logic Block Diagram
300K
XIN 1
8pF
REFERENCE DIVIDER
PD and CP
LF
XOUT 8
8pF
MODULATION CONTROL
VDD 7
VCO COUNTE R
VCO
VSS 2
6
INPUT DECODER LOGIC
3 4
COUNTER and MUX
5
SSCLK
FRSEL
S1
S0
Cypress Semiconductor Corporation Document Number: 38-07112 Rev. *F
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised September 21, 2007
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CY25811/12/14
Pinouts
Figure 1. Pin Diagram - 8 Pin SOIC/TSSOP
XIN/CLKIN 1 VSS 2 S1 3 S0 4 CY25811 CY25812 CY25814
8
XOUT VDD FRSEL SSCLK
7
6
5
Table 1. Pin Definition - 8 Pin SOIC/TSSOP Pin No. Name Type 1 2 3 4 5 6 7 8 Xin/CLK VSS S1 S0 SSCLK FRSEL VDD XOUT Power supply ground.
Description
Crystal, ceramic resonator or clock input pin Digital Spread% control pin. 3-Level input (H-M-L). Default = M. Digital Spread% control pin. 3-Level input (H-M-L). Default = M. Spread Spectrum output clock. Input frequency range selection digital control input. 3-Level input (H-M-L). Default = M. Positive power supply. Crystal or ceramic resonator output pin. Center Spread or Down Spread frequency modulation can be selected by the user based on four discrete values of Spread % for each Spread mode with the option of a Non Spread mode for system test and verification purposes. The CY25811/12/14 products are available in an 8 pin SOIC (150 mil.) package with a commercial operating temperature range of 0 to 70C and Industrial Temperature range of -40 to 85C. Refer to CY25568 for multiple clock output options such as modulated and unmodulated clock outputs or Power-down function. For Automotive applications, refer to CY25811/12/14SE data sheets.
Functional Description
The CY25811/12/14 products are Spread Spectrum Clock Generator (SSCG) ICs used for the purpose of reducing electromagnetic interference (EMI) found in today's high speed digital electronic systems. The devices use a Cypress proprietary phase-locked loop (PLL) and Spread Spectrum Clock (SSC) technology to synthesize and modulate the frequency of the input clock. By frequency modulating the clock, the measured EMI at the fundamental and harmonic frequencies is greatly reduced. This reduction in radiated energy can significantly reduce the cost of complying with regulatory agency requirements and improve time to market without degrading system performance. The input frequency range is 4 to 32 MHz and accepts clock, crystal and ceramic resonator inputs. The output clock can be selected to produce 1x, 2x, or 4x multiplication of the input frequency with Spread Spectrum Frequency Modulation. The use of 2x or 4x frequency multiplication eliminates the need for higher order crystals and enables the user to generate up to 128 MHz Spread Spectrum Clock (SSC) by using only first order crystals. This reduces the cost while improving the system clock accuracy, performance and complexity.
Input Frequency Range and Selection
The CY25811/12/14 input frequency range is 4 to 32 MHz. This range is divided into three segments and controlled by a 3-Level FRSEL pin as given in Table 2. Table 2. Input Frequency Selection FRSEL 0 1 M Input Frequency Range 4.0 to 8.0 MHz 8.0 to 16.0 MHz 16.0 to 32.0 MHz
Document Number: 38-07112 Rev. *F
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CY25811/12/14
Spread% Selection
The CY25811/12/14 SSCG products provide Center-Spread, Down-Spread and No-Spread functions. The amount of Spread% is selected by using 3-Level. S0 and S1 digital inputs and Spread% values are given in Table 3. Table 3. Spread% Selection XIN (MHz) FRSEL S1 = 0 S0 = 0 Center (%) 4-5 5-6 6-7 7-8 8-10 10-12 12-14 14-16 16-20 20-24 24-28 28-32 0 0 0 0 1 1 1 1 M M M M 1.4 1.3 1.2 1.1 1.4 1.3 1.2 1.1 1.4 1.3 1.2 1.1 S1 = 0 S0 = M Center (%) 1.2 1.1 0.9 0.9 1.2 1.1 0.9 0.9 1.2 1.1 0.9 0.9 S1 = 0 S0 = 1 Center (%) 0.6 0.5 0.5 0.4 0.6 0.5 0.5 0.4 0.6 0.5 0.5 0.4 S1 = M S0 = 0 Center (%) 0.5 0.4 0.4 0.3 0.5 0.4 0.4 0.3 0.5 0.4 0.4 0.3 S1 = 1 S0 = 1 Down (%) -3.0 -2.7 -2.5 -2.3 -3.0 -2.7 -2.5 -2.3 -3.0 -2.7 -2.5 -2.3 S1 = 1 S0 = 0 Down (%) -2.2 -1.9 -1.8 -1.7 -2.2 -1.9 -1.8 -1.7 -2.2 -1.9 -1.8 -1.7 S1 = M S0 = 1 Down (%) -1.9 -1.7 -1.5 -1.4 -1.9 -1.7 -1.5 -1.4 -1.9 -1.7 -1.5 -1.4 S1 = 1 S0 = M Down (%) -0.7 -0.6 -0.6 -0.5 -0.7 -0.6 -0.6 -0.5 -0.7 -0.6 -0.6 -0.5 S1 = M S0 = M No Spread 0 0 0 0 0 0 0 0 0 0 0 0
3-Level Digital Inputs
S0, S1, and FRSEL digital inputs are designed to sense 3 different logic levels designated as High "1", Low "0" and Middle "M". With this 3-Level digital input logic, the 3-Level Logic is able to detect 9 different logic states. S0, S1 and FRSEL pins include an on chip 20K (10K/10K) resistor divider. No external application resistors are needed to implement the 3-Level logic levels as shown below: Logic Level "0": 3-Level logic pin connected to GND. Logic Level "M": 3-Level logic pin left floating (no connection). Logic Level "1": 3-Level logic pin connected to VDD. Figure 2 illustrates how to implement 3-Level Logic. Figure 2. 3-Level Logic
LOGIC LOW (0)
S0, S1 and FRSEL to VSS
Modulation Rate
Spread Spectrum Clock Generators utilize frequency modulation (FM) to distribute energy over a specific band of frequencies. The maximum frequency of the clock (fmax), and minimum frequency of the clock (fmin) determine this band of frequencies. The time required to transition from fmin to fmax and back to fmin is the period of the Modulation Rate. The Modulation Rate of SSCG clocks are generally referred to in terms of frequency, or: fmod = 1/Tmod. The input clock frequency, fin, and the internal divider determine the Modulation Rate. In the case of CY25811/2/4 devices, the (Spread Spectrum) modulation Rate, fmod, is given by the following formula: fmod = fin/DR
LOGIC HIGH (H)
S0, S1 and FRSEL to VDD
LOGIC MIDDLE (M)
S0, S1 and FRSEL UNCONNECTED
where: fmod is the Modulation Rate; fin is the Input Frequency; and DR is the Divider Ratio as given in Table 4. Notice that Input Frequency Range is set by FRSEL. Table 4. Modulation Rate Divider Ratios FRSEL 0 Input Frequency Range (MHz) 4 to 8 8 to 16 16 to 32 Divider Ratio (DR) 128 256 512
VSS
1 M
Document Number: 38-07112 Rev. *F
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CY25811/12/14
Input and Output Frequency Selection
The relationship between input frequency versus output frequency in terms of device selection and FRSEL setting is given in Table 5. As shown, the input frequency range is selected by FRSEL and is the same for CY25811, CY25812, and CY25814. The selection of CY25811 (1x), CY25812 (2x) or CY25814 (4x) determines the frequency multiplication at the output (SSCLK, Pin 5) with respect to input frequency (XIN, Pin-1). Table 5. Input and Output Frequency Selection Input Frequency Range (MHz) 4 to 8 8 to 16 16 to 32 4 to 8 8 to 16 16 to 32 4 to 8 8 to 16 16 to 32 FRSEL 0 1 M 0 1 M 0 1 M Product CY25811 CY25811 CY25811 CY25812 CY25812 CY25812 CY25814 CY25814 CY25814 Multiplication 1x 1x 1x 2x 2x 2x 4x 4x 4x Output Frequency Range (MHz) 4 to 8 8 to 16 16 to 32 8 to 16 16 to 32 32 to 64 16 to 32 32 to 64 64 to 128
Document Number: 38-07112 Rev. *F
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CY25811/12/14
Absolute Maximum Conditions (both Commercial and Industrial Grades)[1,2]
Parameter VDD VIN TS TA1 TA2 TJ ESDHBM UL-94 MSL Description Supply Voltage Input Voltage Temperature, Storage Temperature, Operating Ambient Temperature, Operating Ambient Temperature, Junction Flammability Rating Moisture Sensitivity Level Relative to V SS Non Functional Functional, C-Grade Functional, I-Grade Functional @1/8 in. Condition Min -0.5 -0.5 -65 0 -40 - 2000 V-0 1 Max 4.6 VDD + 0.5 150 70 85 150 - Unit V VDC C C C C V
ESD Protection (Human Body Model) MIL-STD-883, Method 3015
DC Electrical Specifications (Commercial Grade)
Parameter VDD VIL VIM VIH VOL1 VOL2 VOH1 VOH2 CIN1 CIN2 CL IDD1 IDD2 IDD3 Description 3.3 Operating Voltage Input Low Voltage Input Middle Voltage Input High Voltage Output Low Voltage Output Low Voltage Output High Voltage Output High Voltage Input Pin Capacitance Input Pin Capacitance Output Load Capacitor Dynamic Supply Current Dynamic Supply Current Dynamic Supply Current 3.3 10% S0, S1 and FRSEL Inputs S0, S1 and FRSEL Inputs S0, S1 and FRSEL Inputs IOL = 4 ma, SSCLK Output IOL = 10 ma, SSCLK Output IOH = 4 ma, SSCLK Output IOH = 6 ma, SSCLK Output XIN (Pin 1) and XOUT (Pin 8) All Digital Inputs SSCLK Output Fin = 12 MHz, no load Fin = 24 MHz, no load Fin = 32 MHz, no load Condition Min 3.97 0 0.85VDD - - 2.4 2.0 3.5 2.8 - - - - Max 3.63 0.15VDD VDD 0.4 1.2 - - 9.0 6.0 15 28 33 40 Unit V V V V V V V V pF pF pF mA mA mA
0.40VDD 0.60VDD
Notes 1. Operation at any Absolute Maximum Rating is not implied. 2. Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power up.
Document Number: 38-07112 Rev. *F
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CY25811/12/14
AC Electrical Specifications (Commercial Grade)
Parameter FIN TR1 TF1 TR2 TF2 TDCIN TDCOUT TCCJ1 TCCJ2 TCCJ3 TCCJ4 TCCJ5 TCCJ6 TSU Description Input Frequency Range Clock Rise Time Clock Fall Time Clock Rise Time Clock Fall Time Input Clock Duty Cycle Output Clock Duty Cycle Cycle to Cycle Jitter, Spread on Cycle to Cycle Jitter, Spread on Cycle to Cycle Jitter, Spread on Cycle to Cycle Jitter, Spread on Cycle to Cycle Jitter, Spread on Cycle to Cycle Jitter, Spread on PLL Lock Time Condition Clock, Crystal, or Ceramic Resonator Input SSCLK, CY25811 and CY25812 SSCLK, CY25811 and CY25812 SSCLK, only CY25814 when FRSEL = M SSCLK, only CY25814 when FRSEL = M XIN SSCLK Fin = 4 MHz, Fout = 4 MHz, CY25811 Fin = 8 MHZ, Fout = 8 MHz, CY25811 Fin = 8 MHz, Fout = 16 MHz, CY25812 Fin = 16 MHz, Fout = 32 MHz, CY25812 Fin = 16 MHz, Fout = 64 MHz, CY25814 Fin = 32 MHz, Fout = 128 MHz, CY25814 Fom VDD 3.0V to valid SSCLK Min 4 2.0 1.6 1.0 0.8 40 40 - - - - - - - Max 32 5.0 4.4 2.2 2.2 60 60 800 480 400 450 550 380 3 Unit MHz ns ns ns ns % % ps ps ps ps ps ps ms
DC Electrical Specifications (Industrial Grade)
Parameter VDD VIL VIM VIH VOL1 VOL2 VOH1 VOH2 CIN1 CIN2 CL IDD1 IDD2 IDD3 Description 3.3 Operating Voltage Input Low Voltage Input Middle Voltage Input High Voltage Output Low Voltage Output Low Voltage Output High Voltage Output High Voltage Input Pin Capacitance Input Pin Capacitance Output Load Capacitor Dynamic Supply Current Dynamic Supply Current Dynamic Supply Current 3.3 5% S0, S1 and FRSEL Inputs S0, S1 and FRSEL Inputs S0, S1 and FRSEL Inputs IOL = 4 ma, SSCLK Output IOL = 10 ma, SSCLK Output IOH = 4 ma, SSCLK Output IOH = 6 ma, SSCLK Output XIN (Pin 1) and XOUT (Pin 8) All Digital Inputs SSCLK Output Fin = 12 MHz, no load Fin = 24 MHz, no load Fin = 32 MHz, no load Condition Min 3.135 0 Max 3.465 0.13VDD Unit V V V V V V V V pF pF pF mA mA mA
0.40VDD 0.60VDD 0.85VDD VDD - - 2.4 2.0 3.5 2.8 - - - - 0.4 1.2 - - 9.0 6.0 15 28 33 41
AC Electrical Specifications (Industrial Grade)
Parameter FIN TR1 TF1 TR2 TF2 TDCIN TDCOUT TCCJ1 Description Input Frequency Range Clock Rise Time Clock Fall Time Clock Rise Time Clock Fall Time Input Clock Duty Cycle Output Clock Duty Cycle Cycle to Cycle Jitter, Spread on Condition Clock, Crystal or Ceramic Resonator Input SSCLK, CY25811, and CY25812 SSCLK, CY25811, and CY25812 SSCLK, only CY25814 when FRSEL = M SSCLK, only CY25814 when FRSEL = M XIN SSCLK Fin = 6MHz, CY25811/12/14 Min 4 2.0 1.6 1.0 0.8 40 40 - Max 32 5.0 4.4 2.2 2.2 60 60 650 Unit MHz ns ns ns ns % % ps Page 6 of 12
Document Number: 38-07112 Rev. *F
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CY25811/12/14
AC Electrical Specifications (Industrial Grade)
Parameter TCCJ2 TCCJ3 TSU Description Cycle-to-Cycle Jitter, Spread on Cycle-to-Cycle Jitter, Spread on PLL Lock Time Condition Fin = 12MHZ, CY25811/12/14 Fin = 24MHz, CY25811/12/14 From VDD 3.0V to valid SSCLK Min - - - Max 630 520 4 Unit ps ps ms
Characteristic Curves
The following curves demonstrate the characteristic behavior of the CY25811/12/14 when tested over a number of environmental and application specific parameters. These are typical performance curves and are not meant to replace any parameter specified in DC and AC Specification tables. Figure 3. Characteristic Curves
600 500
2.75
6.0 MHz 32.0 MHz
2.5
400
CCJ (ps)
BW %
4 8 12 16 20 24 28 32
300 200
2.25
2
100 0
1.75
-40
-25
-10
5
20
35
50
65
80
95
110
125
Input Frequency (MHz)
Temp (C)
Jitter vs. Input Frequency (No Load)
Bandwidth % vs. Temperature
30 28 26 24
IDD (mA)
FRSEL = M 16 - 32 MHz
3 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2 1.9 1.8 2.8
22 20 18 16 14 12 10 4 4.5 5 5.5
FRSEL = 1 8 - 16 MHz
BW (%)
4.0 MHz
8.0 MHz
FRSEL = 0 4 - 8 MHz
6
6.5
7
7.5
8
2.9
3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
Frequency (MHz), no load, normalized to FRSEL = 0, (4 - 8 MHz).
VDD (volts)
IDD vs. Frequency (FRSEL = 0, 1, M)
Bandwidth % vs. VDD
.
Document Number: 38-07112 Rev. *F
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CY25811/12/14
SSCG Profiles
CY25811/12/14 SSCG products use a non-linear "optimized" frequency profile as shown In Figure 4. The use of Cypress proprietary "optimized" frequency profile maintains flat energy distribution over the fundamental and higher order harmonics. This results in additional EMI reduction in electronic systems. Figure 4. Spread Spectrum Profiles (Frequency vs. Time)
Xin = 6.0 MHz S1, S0 = 0 FRSEL = 0
SSCLK1 = 6.0 MHz P/N = CY25811
Xin = 24.0 MHz S1, S0 = 0 FRSEL = M
SSCLK1 = 24.0 MHz P/N = CY25811
Xin = 12.0 MHz S1, S0 = 0 FRSEL = 1
SSCLK1 = 48.0 MHz P/N = CY25814
Xin = 24.0 MHz S1, S0 = 0 FRSEL = M
SSCLK1 = 96.0 MHz P/N = CY25814
Document Number: 38-07112 Rev. *F
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CY25811/12/14
Application Schematic
VDD
C3 0.1 uF
7 C2 1 Y1 25 MHz 8
XIN
VDD
5
27 pF C3
SSCLK XOUT
25 MHz (CY25811) 50 MHz (CY25812) 100 MHz (CY25814)
27 pF
CY25811 CY25812 CY25814
3
S1
6 N/C
FRSEL S0 VSS
2 4
Document Number: 38-07112 Rev. *F
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CY25811/12/14
Ordering Information
Part Number CY25811SCT CY25811SI CY25811SIT CY25812SC CY25812SCT CY25812ZC CY25812ZCT CY25814SCT Pb Free Devices CY25811SXC CY25811SXCT CY25811SXI CY25811SXIT CY25811ZXC CY25811ZXCT CY25812SXC CY25812SXCT CY25812SXI CY25812SXIT CY25812ZXC CY25812ZXCT CY25814SXC CY25814SXCT CY25814SXI CY25814SXIT CY25814ZXC CY25814ZXCT 8-pin SOIC 8-pin SOIC - Tape and Reel 8-pin SOIC 8-pin SOIC - Tape and Reel 8-pin TSSOP 8-pin TSSOP - Tape and Reel 8-pin SOIC 8-pin SOIC - Tape and Reel 8-pin SOIC 8-pin SOIC - Tape and Reel 8-pin TSSOP 8-pin TSSOP - Tape and Reel 8-pin SOIC 8-pin SOIC - Tape and Reel 8-pin SOIC 8-pin SOIC - Tape and Reel 8-pin TSSOP 8-pin TSSOP - Tape and Reel Commercial, 0 to 70C Commercial, 0 to 70C Industrial, -40 to 85C Industrial, -40 to 85C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Industrial, -40 to 85C Industrial, -40 to 85C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Industrial, -40 to 85C Industrial, -40 to 85C Commercial, 0 to 70C Commercial, 0 to 70C 8-pin SOIC 8-pin SOIC - Tape and Reel 8-pin SOIC 8-pin SOIC - Tape and Reel 8-pin TSSOP 8-pin TSSOP - Tape and Reel 8-pin SOIC - Tape and Reel Package Type 8-pin SOIC - Tape and Reel Product Flow Commercial, 0 to 70C Industrial, -40 to 85C Industrial, -40 to 85C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C
Document Number: 38-07112 Rev. *F
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CY25811/12/14
Package Drawing and Dimensions
Figure 5. 8-Pb (150-Mil) SOIC S8
PIN 1 ID
4
1
1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 3. REFERENCE JEDEC MS-012
0.230[5.842] 0.244[6.197]
0.150[3.810] 0.157[3.987]
4. PACKAGE WEIGHT 0.07gms
PART # S08.15 STANDARD PKG. 5 8 SZ08.15 LEAD FREE PKG.
0.189[4.800] 0.196[4.978]
SEATING PLANE
0.010[0.254] 0.016[0.406]
X 45
0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0~8 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249]
0.0138[0.350] 0.0192[0.487]
51-85066-*C
Figure 6. 8-Pb Thin Shrunk Small Outline Package (4.40 MM Body) Z8
PIN 1 ID
1
DIMENSIONS IN MM[INCHES] MIN. MAX.
6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177]
8
0.19[0.007] 0.30[0.012]
0.65[0.025] BSC. 1.10[0.043] MAX.
0.25[0.010] BSC GAUGE PLANE 0-8
0.076[0.003] 0.85[0.033] 0.95[0.037] 2.90[0.114] 3.10[0.122] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027]
51-85093-*A
0.09[[0.003] 0.20[0.008]
Document Number: 38-07112 Rev. *F
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CY25811/12/14(s)
Document History Page
Document Title: CY25811/12/14 Spread Spectrum Clock Generator Document Number: 38-07112 REV. ECN NO. ** *A *B 107516 108002 121578 Issue Date 06/14/02 06/29/02 01/29/03 Orig. of Change NDP NDP RGL Description of Change Converted from IMI to Cypress Deleted Junction Temp. in Absolute Maximum Ratings Converted from Word to FrameMaker Added 8-pin TSSOP package in Commercial Temp. only Added an Industrial Temperature Range to all existing 8-pin SOIC packages Changed IDD values from 19.6/22/27.2 to 25/30/35 in Commercial Grade DC Specs table Changed IDD values from 24/26.5/33 to 26/32/37 in Industrial grade DC Specs table Changed TCCJ1/2 values from 675/260 to 800/450 in Commercial grade AC Specs table Changed TCCJ1 value from 350 to 650 in Industrial grade AC Specs table Removed automotive in the Applications section Changed the Output Clock Duty Cycle (TDCOUT) from min. 45 and max. 55 to 40 and 60% respectively for both industrial and commercial grade Changed the min. Input Low Voltage (VIL) from 0.15VDD to 0.13VDD Removed preliminary from the industrial AC/DC Electrical Specifications table Added Pb Free Devices Updated Ordering Information table Corrected jitter values in features section on page 1 Changed:VDD from 5% to 10%, CIN1 min from 6 to 3.5 pF, CIN2 min from 3.5 to 2.8 pF, TF1 min from 2 to 1.6 ns, and TF2 min from 1.0 to 0.8 ns. Commercial grade: IDD1 max from 25 to 28 mA, IDD2 max from 30 to 33 mA, IDD3 max from 35 to 40 mA, TCCJ2 from 450 to 480 ps, TCCJ4 from 380 to 450 ps, and TCCJ5 from 380 to 550 ps Industrial grade: IDD1 max from 26 to 28 mA, IDD2 max from 32 to 33 mA, IDD3 max from 37 to 41 mA, TCCJ2 from 400 to 630 ps,and TCCJ3 from 400 to 520 ps
*C
125550
05/14/03
RGL
*D
131941
12/24/03
RGL
*E *F
231057
See ECN
RGL KVM
1499165 See ECN
(c) Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-07112 Rev. *F
Revised September 21, 2007
Page 12 of 12
Intel and Pentium are registered trademarks of Intel Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.
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